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| LPC2104/2105/2106 Single-chip 32-bit microcontrollers; 128 kB ISP/IAP flash with 16/32/64 kB RAM Rev. 07 -- 20 June 2008 Product data sheet 1. General description The UART are based on a 16/32-bit ARM7TDMI-S CPU with real-time emulation and embedded trace support, together with 128 kB of embedded high speed flash memory. A 128-bit wide memory interface and a unique accelerator architecture enable 32-bit code execution at maximum clock rate. For critical code size applications, the alternative 16-bit Thumb mode reduces code by more than 30 % with minimal performance penalty. Due to their tiny size and low power consumption, these microcontrollers are ideal for applications where miniaturization is a key requirement, such as access control and point-of-sale. With a wide range of serial communications interfaces and on-chip SRAM options up to 64 kB, they are very well suited for communication gateways and protocol converters, soft modems, voice recognition and low end imaging, providing both large buffer size and high processing power. Various 32-bit timers, PWM channels, and 32 GPIO lines make these microcontrollers particularly suitable for industrial control and medical systems. Remark: Throughout the data sheet, the term LPC2104/2105/2106 will apply to devices with and without /00 and /01 suffixes. Suffixes will be used to differentiate devices whenever they include new features. 2. Features 2.1 New features implemented in LPC2104/2105/2106/01 devices I Fast GPIO port enables port pin toggling up to 3.5 times faster than the original device and also allows for a port pin to be read at any time regardless of its function. I UART 0/1 include fractional baud rate generator, autobauding capabilities, and handshake flow-control fully implemented in hardware. I Buffered SSP serial controller supporting SPI, 4-wire SSI, and Microwire formats. I SPI programmable data length and master mode enhancement. I Diversified Code Read Protection (CRP) enables different security levels to be implemented. I General purpose timers can operate as external event counters. 2.2 Key common features I 16/32-bit ARM7TDMI-S processor. I 16/32/64 kB on-chip static RAM. I 128 kB on-chip flash program memory. 128-bit-wide interface/accelerator enables high speed 60 MHz operation. NXP Semiconductors LPC2104/2105/2106 Single-chip 32-bit microcontrollers I In-System Programming (ISP) and In-Application Programming (IAP) via on-chip bootloader software. Flash programming takes 1 ms per 512 B line. Single sector or full chip erase takes 400 ms. I Vectored Interrupt Controller with configurable priorities and vector addresses. I EmbeddedICE-RT interface enables breakpoints and watch points. Interrupt service routines can continue to execute whilst the foreground task is debugged with the on-chip RealMonitor software. I Embedded Trace Macrocell enables non-intrusive high speed real-time tracing of instruction execution. I Multiple serial interfaces including two UARTs (16C550), Fast I2C-bus (400 kbit/s), and SPI. I Two 32-bit timers (7 capture/compare channels), PWM unit (6 outputs), Real Time Clock and Watchdog. I Up to thirty-two 5 V tolerant general purpose I/O pins in a tiny LQFP48 (7 mm x 7 mm) package. I 60 MHz maximum CPU clock available from programmable on-chip Phase-Locked Loop with settling time of 100 s. I The on-chip crystal oscillator should have an operating range of 1 MHz to 25 MHz. I Two low power modes, Idle and Power-down. I Processor wake-up from Power-down mode via external interrupt. I Individual enable/disable of peripheral functions for power optimization. I Dual power supply: N CPU operating voltage range of 1.65 V to 1.95 V (1.8 V 8.3 %). N I/O power supply range of 3.0 V to 3.6 V (3.3 V 10 %) with 5 V tolerant I/O pads. 3. Ordering information Table 1. Ordering information Package Name LPC2104BBD48 LPC2104FBD48/00 LPC2104FBD48/01 LPC2105BBD48 LPC2105FBD48/00 LPC2105FBD48/01 LPC2106BBD48 LPC2106FBD48 LQFP48 LQFP48 LQFP48 LQFP48 LQFP48 LQFP48 LQFP48 LQFP48 Description plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm Version SOT313-2 SOT313-2 SOT313-2 SOT313-2 SOT313-2 SOT313-2 SOT313-2 SOT313-2 Type number LPC2104_2105_2106_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 20 June 2008 2 of 41 NXP Semiconductors LPC2104/2105/2106 Single-chip 32-bit microcontrollers Ordering information ...continued Package Name Description plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm Version SOT313-2 SOT313-2 SOT619-1 LQFP48 LQFP48 Table 1. Type number LPC2106FBD48/00 LPC2106FBD48/01 LPC2106FHN48 HVQFN48 plastic thermal enhanced very thin quad flat package; no leads; 48 terminals; body 7 x 7 x 0.85 mm HVQFN48 plastic thermal enhanced very thin quad flat package; no leads; 48 terminals; body 7 x 7 x 0.85 mm HVQFN48 plastic thermal enhanced very thin quad flat package; no leads; 48 terminals; body 7 x 7 x 0.85 mm LPC2106FHN48/00 SOT619-1 LPC2106FHN48/01 SOT619-1 3.1 Ordering options Table 2. Ordering options Flash memory 128 kB 128 kB 128 kB 128 kB 128 kB 128 kB 128 kB 128 kB 128 kB 128 kB 128 kB 128 kB 128 kB RAM 16 kB 16 kB 16 kB 32 kB 32 kB 32 kB 64 kB 64 kB 64 kB 64 kB 64 kB 64 kB 64 kB Temperature range 0 C to +70 C -40 C to +85 C -40 C to +85 C 0 C to +70 C -40 C to +85 C -40 C to +85 C 0 C to +70 C -40 C to +85 C -40 C to +85 C -40 C to +85 C -40 C to +85 C -40 C to +85 C -40 C to +85 C Type number LPC2104BBD48 LPC2104FBD48/00 LPC2104FBD48/01 LPC2105BBD48 LPC2105FBD48/00 LPC2105FBD48/01 LPC2106BBD48 LPC2106FBD48 LPC2106FBD48/00 LPC2106FBD48/01 LPC2106FHN48 LPC2106FHN48/00 LPC2106FHN48/01 LPC2104_2105_2106_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 20 June 2008 3 of 41 NXP Semiconductors LPC2104/2105/2106 Single-chip 32-bit microcontrollers 4. Block diagram TMS(2) TDI(2) RTCK TRST(2) TCK(2) TDO(2) XTAL2 XTAL1 RESET EMULATION TRACE MODULE LPC2104/2105/2106 TEST/DEBUG INTERFACE PLL system clock SYSTEM FUNCTIONS VECTORED INTERRUPT CONTROLLER ARM7TDMI-S P0 VDD(3V3) VDD(1V8) VSS HIGH-SPEED GPIO(3) 32 PINS TOTAL AHB BRIDGE ARM7 LOCAL BUS AMBA Advanced High-performance Bus (AHB) INTERNAL SRAM CONTROLLER INTERNAL FLASH CONTROLLER AHB DECODER AHB TO APB BRIDGE APB DIVIDER 16/32/64 kB SRAM 128 kB FLASH Advanced Peripheral Bus (APB) EINT[2:0](1) EXTERNAL INTERRUPTS I2C-BUS SERIAL INTERFACE SCL(1) SDA(1) SCK(1) CAPTURE/ COMPARE TIMER 0/TIMER 1 SPI/SSP(3) SERIAL INTERFACE MOSI(1) MISO(1) SSEL(1) TXD[1:0](1) RXD[1:0](1) CAP0[2:0](1) CAP1[3:0](1) MAT0[2:0](1) MAT1[3:0](1) P0[31:0] GENERAL PURPOSE I/O UART0/UART1 PWM[6:1](1) PWM0 WATCHDOG TIMER DSR1(1), CTS1(1), RTS1(1), DTR1(1), DCD1(1), RI1(1) REAL-TIME CLOCK SYSTEM CONTROL 002aaa412 (1) Shared with GPIO. (2) When test/debug interface is used, GPIO/other functions sharing these pins are not available. (3) Available on LPC2104/2105/2106/01 only. Fig 1. Block diagram LPC2104_2105_2106_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 20 June 2008 4 of 41 NXP Semiconductors LPC2104/2105/2106 Single-chip 32-bit microcontrollers 5. Pinning information 5.1 Pinning 46 P0.16/EINT0/MAT0.2 37 P0.12/DSR1/MAT1.0 36 P0.11/CTS1/CAP1.1 35 P0.10/RTS1/CAP1.0 34 P0.24/PIPESTAT1 33 P0.23/PIPESTAT0 32 P0.22/TRACECLK 31 VSS 30 P0.9/RXD1/PWM6 29 P0.8/TXD1/PWM4 28 P0.7/SSEL/PWM2 27 DBGSEL 26 RTCK 25 n.c. P0.0/TXD0/PWM1 13 P0.1/RXD0/PWM3 14 P0.30/TRACEPKT3/TDI 15 P0.31/EXTIN0/TDO 16 VDD(3V3) 17 P0.2/SCL/CAP0.0 18 VSS 19 n.c. 20 P0.3/SDA/MAT0.0 21 P0.4/SCK/CAP0.1 22 P0.5/MISO/MAT0.1 23 P0.6/MOSI/CAP0.2 24 002aaa411 41 P0.13/DTR1/MAT1.1 47 P0.17/CAP1.2/TRST 39 P0.26/TRACESYNC 48 P0.18/CAP1.3/TMS 44 P0.14/DCD1/EINT1 P0.19/MAT1.2/TCK P0.20/MAT1.3/TDI P0.21/PWM5/TDO n.c. VDD(1V8) RESET VSS P0.27/TRACEPKT0/TRST P0.28/TRACEPKT1/TMS 1 2 3 4 5 6 7 8 9 LPC2104/2105/2106 P0.29/TRACEPKT2/TCK 10 XTAL1 11 XTAL2 12 Pin configuration is identical for all LQFP48 packages. Fig 2. Pin configuration (LQFP48) LPC2104_2105_2106_7 38 P0.25/PIPESTAT2 45 P0.15/RI1/EINT2 40 VDD(3V3) 43 VSS 42 n.c. (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 20 June 2008 5 of 41 NXP Semiconductors LPC2104/2105/2106 Single-chip 32-bit microcontrollers 46 P0.16/EINT0/MAT0.2 terminal 1 index area P0.19/MAT1.2/TCK P0.20/MAT1.3/TDI P0.21/PWM5/TDO n.c. VDD(1V8) RESET VSS P0.27/TRACEPKT0/TRST P0.28/TRACEPKT1/TMS 1 2 3 4 5 6 7 8 9 37 P0.12/DSR1/MAT1.0 36 P0.11/CTS1/CAP1.1 35 P0.10/RTS1/CAP1.0 34 P0.24/PIPESTAT1 33 P0.23/PIPESTAT0 32 P0.22/TRACECLK 31 VSS 30 P0.9/RXD1/PWM6 29 P0.8/TXD1/PWM4 28 P0.7/SSEL/PWM2 27 DBGSEL 26 RTCK 25 n.c. P0.6/MOSI/CAP0.2 24 002aac440 41 P0.13/DTR1/MAT1.1 47 P0.17/CAP1.2/TRST 40 VDD(3V3) 39 P0.26/TRACESYNC P0.3/SDA/MAT0.0 21 P0.4/SCK/CAP0.1 22 48 P0.18/CAP1.3/TMS 44 P0.14/DCD1/EINT1 LPC2104/2105/2106 P0.29/TRACEPKT2/TCK 10 XTAL1 11 XTAL2 12 P0.0/TXD0/PWM1 13 P0.1/RXD0/PWM3 14 P0.30/TRACEPKT3/TDI 15 P0.31/EXTIN0/TDO 16 VDD(3V3) 17 P0.2/SCL/CAP0.0 18 VSS 19 n.c. 20 P0.5/MISO/MAT0.1 23 Transparent top view Pin configuration is identical for LPC2106FHN48, LPC2106FHN48/00, and LPC2106FHN48/01. Fig 3. Pin configuration (HVQFN48) LPC2104_2105_2106_7 38 P0.25/PIPESTAT2 45 P0.15/RI1/EINT2 43 VSS 42 n.c. (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 20 June 2008 6 of 41 NXP Semiconductors LPC2104/2105/2106 Single-chip 32-bit microcontrollers 5.2 Pin description Table 3. Symbol P0.0 to P0.31 Pin description Pin Type I/O Description Port 0: Port 0 is a 32-bit bidirectional I/O port with individual direction controls for each bit. The operation of port 0 pins depends upon the pin function selected via the Pin Connect Block. P0.0 -- Port 0 bit 0. TXD0 -- Transmitter output for UART 0. PWM1 -- Pulse Width Modulator output 1. P0.1 -- Port 0 bit 1. RXD0 -- Receiver input for UART 0. PWM3 -- Pulse Width Modulator output 3. P0.2 -- Port 0 bit 2. The output is open-drain. SCL -- I2C-bus clock input/output. Open-drain output (for I2C-bus compliance). CAP0.0 -- Capture input for Timer 0, channel 0. P0.3 -- Port 0 bit 3. The output is open-drain. SDA -- I2C-bus data input/output. Open-drain output (for I2C-bus compliance). MAT0.0 -- Match output for Timer 0, channel 0. The output is open-drain. P0.4 -- Port 0 bit 4. SCK -- Serial clock for SPI/SSP[3]. Clock output from master or input to slave. CAP0.1 -- Capture input for Timer 0, channel 1. P0.5 -- Port 0 bit 5. MISO -- Master In Slave Out for SPI/SSP[3]. Data input to SPI/SSP master or data output from SPI/SSP slave. MAT0.1 -- Match output for Timer 0, channel 1. P0.6 -- Port 0 bit 6. MOSI -- Master Out Slave In for SPI/SSP[3]. Data output from SPI/SSP master or data input to SPI/SSP slave. CAP0.2 -- Capture input for Timer 0, channel 2. P0.7 -- Port 0 bit 7. SSEL -- Slave Select for SPI/SSP[3]. Selects the SPI/SSP interface as a slave. PWM2 -- Pulse Width Modulator output 2. P0.8 -- Port 0 bit 8. TXD1 -- Transmitter output for UART 1. PWM4 -- Pulse Width Modulator output 4. P0.9 -- Port 0 bit 9. RXD1 -- Receiver input for UART 1. PWM6 -- Pulse Width Modulator output 6. P0.10 -- Port 0 bit 10. RTS1 -- Request to Send output for UART 1. CAP1.0 -- Capture input for Timer 1, channel 0. P0.0/TXD0/PWM1 13[1] I/O O O P0.1/RXD0/PWM3 14[1] I/O I O P0.2/SCL/CAP0.0 18[2] I/O I/O I P0.3/SDA/MAT0.0 21[2] I/O I/O O P0.4/SCK/CAP0.1 22[1] I/O I/O I P0.5/MISO/MAT0.1 23[1] I/O I/O O P0.6/MOSI/CAP0.2 24[1] I/O I/O I P0.7/SSEL/PWM2 28[1] I/O I O P0.8/TXD1/PWM4 29[1] I/O O O P0.9/RXD1/PWM6 30[1] I/O I O P0.10/RTS1/CAP1.0 35[1] I/O O I LPC2104_2105_2106_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 20 June 2008 7 of 41 NXP Semiconductors LPC2104/2105/2106 Single-chip 32-bit microcontrollers Table 3. Symbol Pin description ...continued Pin 36[1] Type I/O I I Description P0.11 -- Port 0 bit 11. CTS1 -- Clear to Send input for UART 1. CAP1.1 -- Capture input for Timer 1, channel 1. P0.12 -- Port 0 bit 12. DSR1 -- Data Set Ready input for UART 1. MAT1.0 -- Match output for Timer 1, channel 0. P0.13 -- Port 0 bit 13. DTR1 -- Data Terminal Ready output for UART 1. MAT1.1 -- Match output for Timer 1, channel 1. P0.14 -- Port 0 bit 14. DCD1 -- Data Carrier Detect input for UART 1. EINT1 -- External interrupt 1 input. P0.15 -- Port 0 bit 15. RI1 -- Ring Indicator input for UART 1. EINT2 -- External interrupt 2 input. P0.16 -- Port 0 bit 16. EINT0 -- External interrupt 0 input. MAT0.2 -- Match output for Timer 0, channel 2. P0.17 -- Port 0 bit 17. CAP1.2 -- Capture input for Timer 1, channel 2. TRST -- Test Reset for JTAG interface, primary JTAG pin group. P0.18 -- Port 0 bit 18. CAP1.3 -- Capture input for Timer 1, channel 3. TMS -- Test Mode Select for JTAG interface, primary JTAG pin group. P0.19 -- Port 0 bit 19. MAT1.2 -- Match output for Timer 1, channel 2. TCK -- Test Clock for JTAG interface, primary JTAG pin group. P0.20 -- Port 0 bit 20. MAT1.3 -- Match output for Timer 1, channel 3. TDI -- Test Data In for JTAG interface, primary JTAG pin group. P0.21 -- Port 0 bit 21. PWM5 -- Pulse Width Modulator output 5. TDO -- Test Data Out for JTAG interface, primary JTAG pin group. P0.22 -- Port 0 bit 22. TRACECLK -- Trace Clock. Standard I/O port with internal pull-up. P0.23 -- Port 0 bit 23. PIPESTAT0 -- Pipeline Status, bit 0. Standard I/O port with internal pull-up. P0.24 -- Port 0 bit 24. PIPESTAT1 -- Pipeline Status, bit 1. Standard I/O port with internal pull-up. P0.25 -- Port 0 bit 25. PIPESTAT2 -- Pipeline Status, bit 2. Standard I/O port with internal pull-up. (c) NXP B.V. 2008. All rights reserved. P0.11/CTS1/CAP1.1 P0.12/DSR1/MAT1.0 37[1] I/O I O P0.13/DTR1/MAT1.1 41[1] I/O O O P0.14/DCD1/EINT1 44[1] I/O I I P0.15/RI1/EINT2 45[1] I/O I O P0.16/EINT0/MAT0.2 46[1] I/O I O P0.17/CAP1.2/TRST 47[1] I/O I I P0.18/CAP1.3/TMS 48[1] I/O I I P0.19/MAT1.2/TCK 1[1] I/O O I P0.20/MAT1.3/TDI 2[1] I/O O I P0.21/PWM5/TDO 3[1] I/O O O P0.22/TRACECLK P0.23/PIPESTAT0 P0.24/PIPESTAT1 P0.25/PIPESTAT2 32[4] 33[4] 34[4] 38[4] I/O O I/O O I/O O I/O O LPC2104_2105_2106_7 Product data sheet Rev. 07 -- 20 June 2008 8 of 41 NXP Semiconductors LPC2104/2105/2106 Single-chip 32-bit microcontrollers Table 3. Symbol Pin description ...continued Pin 39[4] 8[4] Type I/O O I/O O I 9[4] I/O O I 10[4] I/O O I Description P0.26 -- Port 0 bit 26. TRACESYNC -- Trace Synchronization Standard I/O port with internal pull-up. P0.27 -- Port 0 bit 27. TRACEPKT0 -- Trace Packet, bit 0. Standard I/O port with internal pull-up. TRST -- Test Reset for JTAG interface, secondary JTAG pin group. P0.28 -- Port 0 bit 28. TRACEPKT1 -- Trace Packet, bit 1. Standard I/O port with internal pull-up. TMS -- Test Mode Select for JTAG interface, secondary JTAG pin group. P0.29 -- Port 0 bit 29. TRACEPKT2 -- Trace Packet, bit 2. Standard I/O port with internal pull-up. TCK -- Test Clock for JTAG interface, secondary JTAG pin group. This clock must be slower than 1/6 of the CPU clock (CCLK) for the JTAG interface to operate. P0.30 -- Port 0 bit 30. TRACEPKT3 -- Trace Packet, bit 3. Standard I/O port with internal pull-up. TDI -- Test Data In for JTAG interface, secondary JTAG pin group. P0.31 -- Port 0 bit 31. EXTIN0 -- External Trigger Input. Standard I/O port with internal pull-up. TDO -- Test Data out for JTAG interface, secondary JTAG pin group. Returned Test Clock output: Extra signal added to the JTAG port. Assists debugger synchronization when processor frequency varies. Also used during debug mode entry to select primary or secondary JTAG pins with the 48-pin package. Bidirectional pin with internal pull-up. Debug Select: When LOW, the part operates normally. When HIGH, debug mode is entered. Input pin with internal pull-down. external reset input; a LOW on this pin resets the device, causing I/O ports and peripherals to take on their default states, and processor execution to begin at address 0. TTL with hysteresis, 5 V tolerant. input to the oscillator circuit and internal clock generator circuits. output from the oscillator amplifier. ground: 0 V reference. 1.8 V core power supply; this is the power supply voltage for internal circuitry. 3.3 V pad power supply; this is the power supply voltage for the I/O ports. not connected; these pins are not connected in the 48-pin package. P0.26/TRACESYNC P0.27/TRACEPKT0/ TRST P0.28/TRACEPKT1/ TMS P0.29/TRACEPKT2/ TCK P0.30/TRACEPKT3/ TDI 15[4] I/O O I P0.31/EXTIN0/TDO 16[4] I/O I O RTCK 26[4] I/O DBGSEL RESET 27 6[5] I I XTAL1 XTAL2 VSS VDD(1V8) VDD(3V3) n.c. 11 12 7, 19, 31, 43 5 17, 40 4, 20, 25, 42 I O I I I - [1] [2] [3] [4] [5] 5 V tolerant pad providing digital I/O functions with TTL levels and hysteresis and 10 ns slew rate control. Open-drain 5 V tolerant digital I/O pad, compatible with I2C-bus 400 kHz specification. It requires external pull-up to provide an output functionality. Open-drain configuration applies to all functions on this pin. SSP interface available on LPC2104/2105/2106/01 only. 5 V tolerant pad with built-in pull-up resistor providing digital I/O functions with TTL levels and hysteresis and 10 ns slew rate control. The pull-up resistor's value ranges from 60 k to 300 k. 5 V tolerant pad providing digital input (with TTL levels and hysteresis) function only. LPC2104_2105_2106_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 20 June 2008 9 of 41 NXP Semiconductors LPC2104/2105/2106 Single-chip 32-bit microcontrollers 6. Functional description 6.1 Architectural overview The ARM7TDMI-S is a general purpose 32-bit microprocessor, which offers high performance and very low power consumption. The ARM architecture is based on Reduced Instruction Set Computer (RISC) principles, and the instruction set and related decode mechanism are much simpler than those of microprogrammed Complex Instruction Set Computers. This simplicity results in a high instruction throughput and impressive real-time interrupt response from a small and cost-effective processor core. Pipeline techniques are employed so that all parts of the processing and memory systems can operate continuously. Typically, while one instruction is being executed, its successor is being decoded, and a third instruction is being fetched from memory. The ARM7TDMI-S processor also employs a unique architectural strategy known as Thumb, which makes it ideally suited to high-volume applications with memory restrictions, or applications where code density is an issue. The key idea behind Thumb is that of a super-reduced instruction set. Essentially, the ARM7TDMI-S processor has two instruction sets: * The standard 32-bit ARM set. * A 16-bit Thumb set. The Thumb set's 16-bit instruction length allows it to approach twice the density of standard ARM code while retaining most of the ARM's performance advantage over a traditional 16-bit processor using 16-bit registers. This is possible because Thumb code operates on the same 32-bit register set as ARM code. Thumb code is able to provide up to 65 % of the code size of ARM, and 160 % of the performance of an equivalent ARM processor connected to a 16-bit memory system. 6.2 On-chip flash program memory The LPC2104/2105/2106 incorporate a 128 kB flash memory system. This memory may be used for both code and data storage. Programming of the flash memory may be accomplished in several ways. It may be programmed In System via the serial port. The application program may also erase and/or program the flash while the application is running, allowing a great degree of flexibility for data storage field firmware upgrades, etc. When on-chip bootloader is used, 120 kB of flash memory is available for user code. The LPC2104/2105/2106 flash memory provides a minimum of 100000 erase/write cycles and 20 years of data retention. 6.3 On-chip static RAM On-chip static RAM may be used for code and/or data storage. The SRAM may be accessed as 8 bit, 16 bit, and 32 bit. The LPC2104/2105/2106 provide 16/32/64 kB of static RAM, respectively. LPC2104_2105_2106_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 20 June 2008 10 of 41 NXP Semiconductors LPC2104/2105/2106 Single-chip 32-bit microcontrollers 6.4 Memory map The LPC2104/2105/2106 memory maps incorporate several distinct regions, as shown in the following figures. In addition, the CPU interrupt vectors may be re-mapped to allow them to reside in either flash memory (the default) or on-chip static RAM. This is described in Section 6.18 "System control". 4.0 GB AHB PERIPHERALS 3.75 GB APB PERIPHERALS 3.5 GB 0xFFFF FFFF 0xF000 0000 0xEFFF FFFF 0xE000 0000 0xDFFF FFFF 3.0 GB RESERVED ADDRESS SPACE 0xC000 0000 2.0 GB BOOT BLOCK (RE-MAPPED FROM ON-CHIP FLASH MEMORY) 0x8000 0000 0x7FFF FFFF 0x7FFF E000 0x7FFF DFFF RESERVED ADDRESS SPACE 0x4001 0000 0x4000 FFFF 64 kB ON-CHIP STATIC RAM (LPC2106) 0x4000 8000 0x4000 7FFF 32 kB ON-CHIP STATIC RAM (LPC2105) 16 kB ON-CHIP STATIC RAM (LPC2104) 1.0 GB FAST GPIO REGISTERS(1) 0x4000 0000 0x3FFF FFFF 0x3FFF C000 0x4000 4000 0x4000 3FFF RESERVED ADDRESS SPACE 0x0002 0000 0x0001 FFFF 128 kB ON-CHIP FLASH MEMORY 0.0 GB 0x0000 0000 002aad666 (1) LPC2104/2105/2106/01 only. Fig 4. LPC2104/2105/2106 memory map LPC2104_2105_2106_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 20 June 2008 11 of 41 NXP Semiconductors LPC2104/2105/2106 Single-chip 32-bit microcontrollers 6.5 Interrupt controller The Vectored Interrupt Controller (VIC) accepts all of the Interrupt Request (IRQ) inputs and categorizes, them as FIQ, vectored IRQ, and non-vectored IRQ as defined by programmable settings. The programmable assignment scheme means that priorities of interrupts from the various peripherals can be dynamically assigned and adjusted. Fast Interrupt reQuest (FIQ) has the highest priority. If more than one request is assigned to FIQ, the VIC combines the requests to produce the FIQ signal to the ARM processor. The fastest possible FIQ latency is achieved when only one request is classified as FIQ, because then the FIQ service routine can simply start dealing with that device. But if more than one request is assigned to the FIQ class, the FIQ service routine can read a word from the VIC that identifies which FIQ source(s) is (are) requesting an interrupt. Vectored IRQs have the middle priority. Sixteen of the interrupt requests can be assigned to this category. Any of the interrupt requests can be assigned to any of the 16 vectored IRQ slots, among which slot 0 has the highest priority and slot 15 has the lowest. Non-vectored IRQs have the lowest priority. The VIC combines the requests from all the vectored and non-vectored IRQs to produce the IRQ signal to the ARM processor. The IRQ service routine can start by reading a register from the VIC and jumping there. If any of the vectored IRQs are requesting, the VIC provides the address of the highest-priority requesting IRQs service routine, otherwise it provides the address of a default routine that is shared by all the non-vectored IRQs. The default routine can read another VIC register to see what IRQs are active. 6.5.1 Interrupt sources Table 4 lists the interrupt sources for each peripheral function. Each peripheral device has one interrupt line connected to the Vectored Interrupt Controller, but may have several internal interrupt flags. Individual interrupt flags may also represent more than one interrupt source. Table 4. Block WDT ARM Core ARM Core Timer 0 Timer 1 UART 0 Interrupt sources Flag(s) Watchdog Interrupt (WDINT) Reserved for software interrupts only EmbeddedICE, DbgCommRx EmbeddedICE, DbgCommTx Match 0 to 3 (MR0, MR1, MR2, MR3) Capture 0 to 2 (CR0, CR1, CR2) Match 0 to 3 (MR0, MR1, MR2, MR3) Capture 0 to 3 (CR0, CR1, CR2, CR3) Rx Line Status (RLS) Transmit Holding Register empty (THRE) Rx Data Available (RDA) Character Time-out Indicator (CTI) Auto-Baud Time-Out (ABTO)[1] End of Auto-Baud (ABEO)[1] 6 5 VIC channel # 0 1 2 3 4 LPC2104_2105_2106_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 20 June 2008 12 of 41 NXP Semiconductors LPC2104/2105/2106 Single-chip 32-bit microcontrollers Interrupt sources ...continued Flag(s) Rx Line Status (RLS) Transmit Holding Register empty (THRE) Rx Data Available (RDA) Character Time-out Indicator (CTI) Modem Status Interrupt (MSI) Auto-Baud Time-Out (ABTO)[1] End of Auto-Baud (ABEO)[1] VIC channel # 7 Table 4. Block UART 1 PWM0 I2C-bus SPI and PLL RTC System Control System Control System Control [1] Match 0 to 6 (MR0, MR1, MR2, MR3, MR4, MR5, MR6) SI (state change) SSP[1] SPIF, MODF (SPI) TXRIS, RXRIS, RTRIS, RORRIS (SSP)[1] reserved PLL Lock (PLOCK) RTCCIF (Counter Increment), RTCALF (Alarm) External Interrupt 0 (EINT0) External Interrupt 1 (EINT1) External Interrupt 2 (EINT2) 8 9 10 11 12 13 14 15 16 Available on LPC2104/2105/2106/01 only. 6.6 Pin connect block The pin connect block allows selected pins of the microcontroller to have more than one function. Configuration registers control the multiplexers to allow connection between the pin and the on chip peripherals. Peripherals should be connected to the appropriate pins prior to being activated, and prior to any related interrupt(s) being enabled. Activity of any enabled peripheral function that is not mapped to a related pin should be considered undefined. The Pin Control Module contains two registers as shown in Table 5. Table 5. Address 0xE002 C000 0xE002 C004 Pin control module registers Name PINSEL0 PINSEL1 Description Pin function select register 0 Pin function select register 1 Access Read/Write Read/Write 6.7 Pin function select register 0 (PINSEL0 - 0xE002 C000) The PINSEL0 register controls the functions of the pins as per the settings listed in Table 6. The direction control bit in the IODIR register is effective only when the GPIO function is selected for a pin. For other functions, direction is controlled automatically. Settings other than those shown in Table 6 are reserved, and should not be used LPC2104_2105_2106_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 20 June 2008 13 of 41 NXP Semiconductors LPC2104/2105/2106 Single-chip 32-bit microcontrollers Pin function select register 0 (PINSEL0 - 0xE002 C000) Pin name P0.0 Value 0 0 1 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 Function GPIO Port 0.0 TXD (UART 0) PWM1 GPIO Port 0.1 RXD (UART 0) PWM3 GPIO Port 0.2 SCL (I2C-bus) 0 Capture 0.0 (Timer 0) GPIO Port 0.3 SDA (I2C-bus) Match 0.0 (Timer 0) GPIO Port 0.4 SCK (SPI/SSP) Capture 0.1 (Timer 0) GPIO Port 0.5 MISO (SPI/SSP) Match 0.1 (Timer 0) GPIO Port 0.6 MOSI (SPI/SSP) Capture 0.2 (Timer 0) GPIO Port 0.7 SSEL (SPI/SSP) PWM2 GPIO Port 0.8 TXD (UART 1) PWM4 GPIO Port 0.9 RXD (UART 1) PWM6 GPIO Port 0.10 RTS (UART 1) Capture 1.0 (Timer 1) GPIO Port 0.11 CTS (UART 1) Capture 1.1 (Timer 1) GPIO Port 0.12 DSR (UART 1) Match 1.0 (Timer 1) 0 0 0 0 0 0 0 0 0 0 0 Value after reset 0 Table 6. PINSEL0 1:0 3:2 P0.1 0 0 1 5:4 P0.2 0 0 1 7:6 P0.3 0 0 1 9:8 P0.4 0 0 1 11:10 P0.5 0 0 1 13:12 P0.6 0 0 1 15:14 P0.7 0 0 1 17:16 P0.8 0 0 1 19:18 P0.9 0 0 1 21:20 P0.10 0 0 1 23:22 P0.11 0 0 1 25:24 P0.12 0 0 1 LPC2104_2105_2106_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 20 June 2008 14 of 41 NXP Semiconductors LPC2104/2105/2106 Single-chip 32-bit microcontrollers Pin function select register 0 (PINSEL0 - 0xE002 C000) ...continued Pin name P0.13 Value 0 0 1 0 1 0 0 1 0 0 1 0 Function GPIO Port 0.13 DTR (UART 1) Match 1.1 (Timer 1) GPIO Port 0.14 DCD (UART 1) EINT1 GPIO Port 0.15 RI (UART 1) EINT2 0 0 Value after reset 0 Table 6. PINSEL0 27:26 29:28 P0.14 0 0 1 31:30 P0.15 0 0 1 6.8 Pin function select register 1 (PINSEL1 - 0xE002 C004) The PINSEL1 register controls the functions of the pins as per the settings listed in Table 7. The direction control bit in the IODIR register is effective only when the GPIO function is selected for a pin. For other functions direction is controlled automatically. Remark: The primary JTAG port and the trace port can be selected only through the DBGSEL pin at reset (Debug mode). Function control for the pins P0[31:17] is effective only when the DBGSEL input is pulled LOW during reset. Table 7. PINSEL1 1:0 Pin function select register 1 (PINSEL1 - 0xE002 C004) Pin name P0.16 Value 0 0 1 3:2 5:4 7:6 9:8 11:10 13:12 15:14 17:16 19:18 21:20 23:22 P0.17 P0.18 P0.19 P0.20 P0.21 P0.22 P0.23 P0.24 P0.25 P0.26 P0.27 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 1 Function GPIO Port 0.16 EINT0 Match 0.2 (Timer 0) GPIO Port 0.17 Capture 1.2 (Timer 1) GPIO Port 0.18 Capture 1.3 (Timer 1) GPIO Port 0.19 Match 1.2 (Timer 1) GPIO Port 0.20 Match 1.3 (Timer 1) GPIO Port 0.21 PWM5 GPIO Port 0.22 GPIO Port 0.23 GPIO Port 0.24 GPIO Port 0.25 GPIO Port 0.26 GPIO Port 0.27 TRST 0 0 0 0 0 0 0 0 0 0 0 Value after reset 0 LPC2104_2105_2106_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 20 June 2008 15 of 41 NXP Semiconductors LPC2104/2105/2106 Single-chip 32-bit microcontrollers Pin function select register 1 (PINSEL1 - 0xE002 C004) ...continued Pin name P0.28 P0.29 P0.30 P0.31 Value 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 Function GPIO Port 0.28 TMS GPIO Port 0.29 TCK GPIO Port 0.30 TDI GPIO Port 0.31 TDO 0 0 0 Value after reset 0 Table 7. PINSEL1 25:24 27:26 29:28 31:30 6.9 General purpose parallel I/O Device pins that are not connected to a specific peripheral function are controlled by the GPIO registers. Pins may be dynamically configured as inputs or outputs. Separate registers allow setting or clearing any number of outputs simultaneously. The value of the output register may be read back, as well as the current state of the port pins. 6.9.1 Features * Direction control of individual bits. * Separate control of output set and clear. * All I/O default to inputs after reset. 6.9.2 Features added with the Fast GPIO set of registers available on LPC2104/2105/2106/01 only * Fast GPIO registers are relocated to the ARM local bus for the fastest possible I/O timing, enabling port pin toggling up to 3.5 times faster than earlier LPC2000 devices. * Mask registers allow treating sets of port bits as a group, leaving other bits unchanged. * All Fast GPIO registers are byte addressable. * Entire port value can be written in one instruction. * Ports are accessible via either the legacy group of registers (GPIOs) or the group of registers providing accelerated port access (Fast GPIOs). 6.10 UARTs The LPC2104/2105/2106 each contain two UARTs. One UART provides a full modem control handshake interface, the other provides only transmit and receive data lines. 6.10.1 Features * * * * LPC2104_2105_2106_7 16 byte Receive and Transmit FIFOs Register locations conform to 16C550 industry standard Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B Built-in baud rate generator (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 20 June 2008 16 of 41 NXP Semiconductors LPC2104/2105/2106 Single-chip 32-bit microcontrollers * Standard modem interface signals included on UART 1. 6.10.2 UART features available in LPC2104/2105/2106/01 only Compared to previous LPC2000 microcontrollers, UARTs in LPC2104/2105/2106/01 introduce a fractional baud rate generator for both UARTs, enabling these microcontrollers to achieve standard baud rates such as 115200 Bd with any crystal frequency above 2 MHz. In addition, auto-CTS/RTS flow-control functions are fully implemented in hardware. * Fractional baud rate generator enables standard baud rates such as 115200 Bd to be achieved with any crystal frequency above 2 MHz. * Autobauding. * Auto-CTS/RTS flow-control fully implemented in hardware. 6.11 I2C-bus serial I/O controller I2C is a bidirectional bus for inter-IC control using only two wires: a serial clock line (SCL), and a serial data line (SDA). Each device is recognized by a unique address and can operate as either a receiver-only device (e.g. an LCD driver or a transmitter with the capability to both receive and send information (such as memory). Transmitters and/or receivers can operate in either master or slave mode, depending on whether the chip has to initiate a data transfer or is only addressed. I2C is a multi-master bus, it can be controlled by more than one bus master connected to it. The I2C-bus implemented in LPC2104/2105/2106 supports bit rate up to 400 kbit/s (Fast I2C-bus). 6.11.1 Features * Standard I2C compliant bus interface. * Easy to configure as Master, Slave or Master/Slave. * Programmable clocks allow versatile rate control. * Bidirectional data transfer between masters and slaves. * Multi-master bus (no central master). * Arbitration between simultaneously transmitting masters without corruption of serial data on the bus. * Serial clock synchronization allows devices with different bit rates to communicate via one serial bus. * Serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer. * The I2C-bus may be used for test and diagnostic purposes. LPC2104_2105_2106_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 20 June 2008 17 of 41 NXP Semiconductors LPC2104/2105/2106 Single-chip 32-bit microcontrollers 6.12 SPI serial I/O controller The SPI is a full duplex serial interface, designed to be able to handle multiple masters and slaves connected to a given bus. Only a single master and a single slave can communicate on the interface during a given data transfer. During a data transfer the master always sends a byte of data to the slave, and the slave always sends a byte of data to the master. 6.12.1 Features * Compliant with Serial Peripheral Interface (SPI) specification. * Synchronous, serial, full duplex communication. * Combined SPI master and slave. * Maximum data bit rate of one eighth of the input clock rate. 6.12.2 Features available in LPC2104/2105/2106/01 only * Selectable transfer width of eight to 16 bit per frame. * When the SPI interface is used in Master mode, the SSEL pin is not needed (can be used for a different function). 6.13 SSP controller (LPC2104/2015/2106/01 only) The SSP is a controller capable of operation on a SPI, 4-wire SSI, or Microwire bus. It can interact with multiple masters and slaves on the bus. Only a single master and a single slave can communicate on the bus during a given data transfer. Data transfers are in principle full duplex, with frames of four to 16 bits of data flowing from the master to the slave and from the slave to the master. Because the SSP and SPI peripherals share the same physical pins, it is not possible to have both of these two peripherals active at the same time. Application can switch on the fly from SPI to SSP and back. 6.13.1 Features * Compatible with Motorola's SPI, Texas Instrument's 4-wire SSI, and National Semiconductor's Microwire buses. * * * * Synchronous serial communication. Master or slave operation. 8-frame FIFOs for both transmit and receive. Four to 16 bits per frame. 6.14 General purpose timers The Timer is designed to count cycles of the peripheral clock (PCLK) and optionally generate interrupts or perform other actions at specified timer values, based on four match registers. It also includes up to four capture inputs to trap the timer value when an input signal transitions, optionally generating an interrupt. LPC2104_2105_2106_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 20 June 2008 18 of 41 NXP Semiconductors LPC2104/2105/2106 Single-chip 32-bit microcontrollers 6.14.1 Features * A 32-bit Timer/Counter with a programmable 32-bit Prescaler. * Up to four (Timer 1) and three (Timer 0) 32-bit capture channels, that can take a snapshot of the timer value when an input signal transitions. A capture event may also optionally generate an interrupt. * Four 32-bit match registers that allow: - Continuous operation with optional interrupt generation on match. - Stop timer on match with optional interrupt generation. - Reset timer on match with optional interrupt generation. * Up to four (Timer 1) and three (Timer 0) external outputs corresponding to match registers, with the following capabilities: - Set LOW on match. - Set HIGH on match. - Toggle on match. - Do nothing on match. 6.14.2 Features available in LPC2104/2105/2106/01 only The LPC2104/2105/2106/01 can count external events on one of the capture inputs if the external pulse lasts at least one half of the period of the PCLK. In this configuration, unused capture lines can be selected as regular timer capture inputs or used as external interrupts. * Timer can count cycles of either the peripheral clock (PCLK) or an externally supplied clock. * When counting cycles of an externally supplied clock, only one of the timer's capture inputs can be selected as the timer's clock. The rate of such a clock is limited to PCLK . Duration of HIGH/LOW levels on the selected CAP input cannot be shorter 4 than 1(2PCLK). 6.15 Watchdog timer The purpose of the Watchdog is to reset the microcontroller within a reasonable amount of time if it enters an erroneous state. When enabled, the Watchdog will generate a system reset if the user program fails to `feed' (or reload) the Watchdog within a predetermined amount of time. 6.15.1 Features * Internally resets chip if not periodically reloaded. * Debug mode. * Enabled by software but requires a hardware reset or a watchdog reset/interrupt to be disabled. * Incorrect/Incomplete feed sequence causes reset/interrupt if enabled. * Flag to indicate watchdog reset. LPC2104_2105_2106_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 20 June 2008 19 of 41 NXP Semiconductors LPC2104/2105/2106 Single-chip 32-bit microcontrollers * Programmable 32-bit timer with internal pre-scaler. * Selectable time period from (Tcy(PCLK) x 256 x 4) to (Tcy(PCLK) x 232 x 4) in multiples of Tcy(PCLK) x 4. 6.16 Real time clock The Real Time Clock (RTC) is designed to provide a set of counters to measure time when normal or idle operating mode is selected. The RTC has been designed to use little power, making it suitable for battery powered systems where the CPU is not running continuously (Idle mode). 6.16.1 Features * Measures the passage of time to maintain a calendar and clock. * Ultra Low Power design to support battery powered systems. * Provides Seconds, Minutes, Hours, Day of Month, Month, Year, Day of Week, and Day of Year. * Programmable Reference Clock Divider allows adjustment of the RTC to match various crystal frequencies. 6.17 Pulse width modulator The PWM is based on the standard Timer block and inherits all of its features, although only the PWM function is pinned out on the LPC2104/2105/2106. The Timer is designed to count cycles of the peripheral clock (PCLK) and optionally generate interrupts or perform other actions when specified timer values occur, based on seven match registers. It also includes four capture inputs to save the timer value when an input signal transitions, and optionally generate an interrupt when those events occur. The PWM function is in addition to these features, and is based on match register events. The ability to separately control rising and falling edge locations allows the PWM to be used for more applications. For instance, multi-phase motor control typically requires three non-overlapping PWM outputs with individual control of all three pulse widths and positions. Two match registers can be used to provide a single edge controlled PWM output. One match register (MR0) controls the PWM cycle rate, by resetting the count upon match. The other match register controls the PWM edge position. Additional single edge controlled PWM outputs require only one match register each, since the repetition rate is the same for all PWM outputs. Multiple single edge controlled PWM outputs will all have a rising edge at the beginning of each PWM cycle, when an MR0 match occurs. Three match registers can be used to provide a PWM output with both edges controlled. Again, the MR0 match register controls the PWM cycle rate. The other match registers control the two PWM edge positions. Additional double edge controlled PWM outputs require only two match registers each, since the repetition rate is the same for all PWM outputs. LPC2104_2105_2106_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 20 June 2008 20 of 41 NXP Semiconductors LPC2104/2105/2106 Single-chip 32-bit microcontrollers With double edge controlled PWM outputs, specific match registers control the rising and falling edge of the output. This allows both positive going PWM pulses (when the rising edge occurs prior to the falling edge), and negative going PWM pulses (when the falling edge occurs prior to the rising edge). 6.17.1 Features * Seven match registers allow up to six single edge controlled or three double edge controlled PWM outputs, or a mix of both types. * The match registers also allow: - Continuous operation with optional interrupt generation on match. - Stop timer on match with optional interrupt generation. - Reset timer on match with optional interrupt generation. * Supports single edge controlled and/or double edge controlled PWM outputs. Single edge controlled PWM outputs all go HIGH at the beginning of each cycle unless the output is a constant LOW. Double edge controlled PWM outputs can have either edge occur at any position within a cycle. This allows for both positive going and negative going pulses. * Pulse period and width can be any number of timer counts. This allows complete flexibility in the trade-off between resolution and repetition rate. All PWM outputs will occur at the same repetition rate. * Double edge controlled PWM outputs can be programmed to be either positive going or negative going pulses. * Match register updates are synchronized with pulse outputs to prevent generation of erroneous pulses. Software must "release" new match values before they can become effective. * May be used as a standard timer if the PWM mode is not enabled. * A 32-bit Timer/Counter with a programmable 32-bit Prescaler. 6.18 System control 6.18.1 Crystal oscillator The oscillator supports crystals in the range of 1 MHz to 25 MHz. The oscillator output frequency is called FOSC and the ARM processor clock frequency is referred to as CCLK for purposes of rate equations, etc. FOSC and CCLK are the same value unless the PLL is running and connected. Refer to Section 6.18.2 "PLL" for additional information. 6.18.2 PLL The PLL accepts an input clock frequency in the range of 10 MHz to 25 MHz. The input frequency is multiplied up into the range of 10 MHz to 60 MHz with a Current Controlled Oscillator (CCO). The multiplier can be an integer value from 1 to 32 (in practice, the multiplier value cannot be higher than 6 on this family of microcontrollers due to the upper frequency limit of the CPU). The CCO operates in the range of 156 MHz to 320 MHz, so there is an additional divider in the loop to keep the CCO within its frequency range while the PLL is providing the desired output frequency. The output divider may be set to divide LPC2104_2105_2106_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 20 June 2008 21 of 41 NXP Semiconductors LPC2104/2105/2106 Single-chip 32-bit microcontrollers by 2, 4, 8, or 16 to produce the output clock. Since the minimum output divider value is 2, it is insured that the PLL output has a 50 % duty cycle.The PLL is turned off and bypassed following a chip Reset and may be enabled by software. The program must configure and activate the PLL, wait for the PLL to Lock, then connect to the PLL as a clock source. The PLL settling time is 100 s. 6.18.3 Reset and wake-up timer Reset has two sources on the LPC2104/2105/2106: the RESET pin and Watchdog Reset. The RESET pin is a Schmitt trigger input pin with an additional glitch filter. Assertion of chip Reset by any source starts the wake-up timer (see wake-up timer description below), causing the internal chip reset to remain asserted until the external Reset is de-asserted, the oscillator is running, a fixed number of clocks have passed, and the on-chip flash controller has completed its initialization. When the internal Reset is removed, the processor begins executing at address 0, which is the Reset vector. At that point, all of the processor and peripheral registers have been initialized to predetermined values. The wake-up timer ensures that the oscillator and other analog functions required for chip operation are fully functional before the processor is allowed to execute instructions. This is important at power on, all types of Reset, and whenever any of the aforementioned functions are turned off for any reason. Since the oscillator and other functions are turned off during Power-down mode, any wake-up of the processor from Power-down mode makes use of the wake-up timer. The wake-up timer monitors the crystal oscillator as the means of checking whether it is safe to begin code execution. When power is applied to the chip, or some event caused the chip to exit Power-down mode, some time is required for the oscillator to produce a signal of sufficient amplitude to drive the clock logic. The amount of time depends on many factors, including the rate of VDD ramp (in the case of power on), the type of crystal and its electrical characteristics (if a quartz crystal is used), as well as any other external circuitry (e.g. capacitors), and the characteristics of the oscillator itself under the existing ambient conditions. 6.18.4 Code security (Code Read Protection - CRP) This feature of the LPC2104/2105/2106/01 allows the user to enable different levels of security in the system so that access to the on-chip flash and use of the JTAG and ISP can be restricted. When needed, CRP is invoked by programming a specific pattern into a dedicated flash location. IAP commands are not affected by the CRP. There are three levels of the Code Read Protection: 1. CRP1 disables access to the chip via the JTAG and allows partial flash update (excluding flash sector 0) using a limited set of the ISP commands. This mode is useful when CRP is required and flash field updates are needed but all sectors can not be erased. 2. CRP2 disables access to the chip via the JTAG and only allows full flash erase and update using a reduced set of the ISP commands. LPC2104_2105_2106_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 20 June 2008 22 of 41 NXP Semiconductors LPC2104/2105/2106 Single-chip 32-bit microcontrollers 3. Running an application with level CRP3 selected fully disables any access to chip via the JTAG pins and the ISP. This mode effectively disables ISP override using P0[14] pin, too. It is up to the user's application to provide (if needed) a flash update mechanism using IAP calls or a call to reinvoke ISP command to enable flash update via UART 0. CAUTION If level three Code Read Protection (CRP3) is selected, no future factory testing can be performed on the device. 6.18.5 External interrupt inputs The LPC2104/2105/2106 include three external interrupt inputs as selectable pin functions. The external interrupt inputs can optionally be used to wake up the processor from Power-down mode. 6.18.6 Memory mapping control The Memory mapping control alters the mapping of the interrupt vectors that appear beginning at address 0x0000 0000. Vectors may be mapped to the bottom of the on-chip flash memory, or to the on-chip static RAM. This allows code running in different memory spaces to have control of the interrupts. 6.18.7 Power control The LPC2104/2105/2106 support two reduced power modes: Idle mode and Power-down mode. In Idle mode, execution of instructions is suspended until either a Reset or interrupt occurs. Peripheral functions continue operation during Idle mode and may generate interrupts to cause the processor to resume execution. Idle mode eliminates power used by the processor itself, memory systems and related controllers, and internal buses. In Power-down mode, the oscillator is shut down and the chip receives no internal clocks. The processor state and registers, peripheral registers, and internal SRAM values are preserved throughout Power-down mode and the logic levels of chip output pins remain static. The Power-down mode can be terminated and normal operation resumed by either a Reset or certain specific interrupts that are able to function without clocks. Since all dynamic operation of the chip is suspended, Power-down mode reduces chip power consumption to nearly zero. The power can be controlled for each peripheral individually allowing peripherals to be turned off if they are not needed in the application and resulting in additional power savings. 6.18.8 APB The APB divider determines the relationship between the processor clock (CCLK) and the clock used by peripheral devices (PCLK). The APB divider serves two purposes. The first is to provide peripherals with the desired PCLK via APB so that they can operate at the speed chosen for the ARM processor. In order to achieve this, the APB may be slowed down to 12 to 14 of the processor clock rate. Because the APB must work properly at power-up (and its timing cannot be altered if it does not work since the APB divider control registers reside on the APB), the default condition at reset is for the APB to run at 14 of the LPC2104_2105_2106_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 20 June 2008 23 of 41 NXP Semiconductors LPC2104/2105/2106 Single-chip 32-bit microcontrollers processor clock rate. The second purpose of the APB divider is to allow power savings when an application does not require any peripherals to run at the full processor rate. Because the APB divider is connected to the PLL output, the PLL remains active (if it was running) during Idle mode. 6.19 Emulation and debugging The LPC2104/2105/2106 support emulation and debugging via a JTAG serial port. A trace port allows tracing program execution. Each of these functions requires a trade-off of debugging features versus device pins. Because the LPC2104/2105/2106 are provided in a small package, there is no room for permanently assigned JTAG or Trace pins. An alternate JTAG port allows an option to debug functions assigned to the pins used by the primary JTAG port (see Section 6.8). 6.19.1 EmbeddedICE Standard ARM EmbeddedICE logic provides on-chip debug support. The debugging of the target system requires a host computer running the debugger software and an EmbeddedICE protocol convertor. EmbeddedICE protocol convertor converts the Remote Debug Protocol commands to the JTAG data needed to access the ARM core. The ARM core has a Debug Communication Channel function built-in. The debug communication channel allows a program running on the target to communicate with the host debugger or another separate host without stopping the program flow or even entering the debug state. The debug communication channel is accessed as a co-processor 14 by the program running on the ARM7TDMI-S core. The debug communication channel allows the JTAG port to be used for sending and receiving data without affecting the normal program flow. The debug communication channel data and control registers are mapped in to addresses in the EmbeddedICE logic. The JTAG clock (TCK) must be slower than 16 of the CPU clock (CCLK) for the JTAG interface to operate. 6.19.2 Embedded trace Since the LPC2104/2105/2106 have significant amounts of on-chip memory, it is not possible to determine how the processor core is operating simply by observing the external pins. The Embedded Trace Macrocell (ETM) provides real-time trace capability for deeply embedded processor cores. It outputs information about processor execution to the trace port. The ETM is connected directly to the ARM core and not to the main AMBA system bus. It compresses the trace information and exports it through a narrow trace port. An external trace port analyzer must capture the trace information under software debugger control. Instruction trace (or PC trace) shows the flow of execution of the processor and provides a list of all the instructions that were executed. Instruction trace is significantly compressed by only broadcasting branch addresses as well as a set of status signals that indicate the pipeline status on a cycle by cycle basis. Trace information generation can be controlled by selecting the trigger resource. Trigger resources include address comparators, counters and sequencers. Since trace information is compressed the software debugger requires a static image of the code being executed. Self-modifying code cannot be traced because of this restriction. LPC2104_2105_2106_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 20 June 2008 24 of 41 NXP Semiconductors LPC2104/2105/2106 Single-chip 32-bit microcontrollers 6.19.3 RealMonitor RealMonitor is a configurable software module, developed by ARM Inc., which enables real time debug. It is a lightweight debug monitor that runs in the background while users debug their foreground application. It communicates with the host using the DCC (Debug Communications Channel), which is present in the EmbeddedICE logic. The LPC2104/2105/2106 contain a specific configuration of RealMonitor software programmed into the on-chip flash memory. LPC2104_2105_2106_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 20 June 2008 25 of 41 NXP Semiconductors LPC2104/2105/2106 Single-chip 32-bit microcontrollers 7. Limiting values Table 8. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134).[1] Symbol VDD(1V8) VDD(3V3) VI IDD ISS Tstg Ptot(pack) Parameter supply voltage (1.8 V) supply voltage (3.3 V) input voltage supply current ground current storage temperature total power dissipation (per package) electrostatic discharge voltage based on package heat transfer, not device power consumption human body model all pins machine model all pins [1] [12] [11] Conditions [2] [3] Min -0.5 -0.5 -0.5 -0.5 -65 - Max +2.5 +3.6 +6.0 VDD(3V3) + 0.5 100 100 +150 1.5 Unit V V V V mA mA C W 5 V tolerant I/O pins other I/O pins [4][5] [4][6] [7][8] [8][9] [10] Vesd -2000 -200 +2000 +200 V V The following applies to Table 8: a) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum. b) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise noted. Internal rail. External rail. Including voltage on outputs in 3-state mode. Only valid when the VDD(3V3) supply voltage is present. Not to exceed 4.6 V. Per supply pin. The peak current is limited to 25 times the corresponding maximum current. Per ground pin. [2] [3] [4] [5] [6] [7] [8] [9] [10] Dependent on package type. [11] Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 k series resistor. [12] Machine model: equivalent to discharging a 200 pF capacitor through a 0.75 H coil and a 10 series resistor. LPC2104_2105_2106_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 20 June 2008 26 of 41 NXP Semiconductors LPC2104/2105/2106 Single-chip 32-bit microcontrollers 8. Static characteristics Table 9. Static characteristics Tamb = 0 C to +70 C for commercial applications, unless otherwise specified. Symbol VDD(1V8) VDD(3V3) IIL IIH IOZ Ilatch VI VO VIH VIL Vhys VOH VOL IOH IOL IOHS IOLS Ipd Ipu Parameter supply voltage (1.8 V) supply voltage (3.3 V) LOW-state input current HIGH-state input current OFF-state output current I/O latch-up current input voltage output voltage HIGH-state input voltage LOW-state input voltage hysteresis voltage HIGH-state output voltage LOW-state output voltage HIGH-state output current LOW-state output current HIGH-state short-circuit output current LOW-state short-circuit output current pull-down current pull-up current IOH = -4 mA IOL = 4 mA VOH = VDD(3V3) - 0.4 V VOL = 0.4 V VOH = 0 V VOL = VDD(3V3) VI = 5 V; applies to DBGSEL VI = 0 V VDD(3V3) < VI < 5 V LPC2104/2105/2106/01 Ipu pull-up current VI = 0 V VDD(3V3) < VI < 5 V [10] [9][10] [7] [7] [7] [7] [8] Conditions [2] [3] Min 1.65 3.0 100 [4][5] [6] Typ[1] 1.8 3.3 0.4 50 -50 0 -50 0 Max 1.95 3.6 3 3 3 5.5 VDD(3V3) 0.8 0.4 -45 50 100 -65 0 -85 0 Unit V V A A A mA V V V V V V V mA mA mA mA A A A A A Standard port pins, RESET, RTCK, and DBGSEL VI = 0 V; no pull-up VI = VDD(3V3); no pull-down VO = 0 V, VO = VDD(3V3); no pull-up/down -(0.5VDD(3V3)) < VI < (1.5VDD(3V3)); Tj < 125 C 0 0 2.0 -4 4 20 -25 0 -15 0 output active VDD(3V3) - 0.4 - [8] [9] LPC2104/2105/2106 and LPC2104/2105/2106/00 [10] [9][10] LPC2104_2105_2106_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 20 June 2008 27 of 41 NXP Semiconductors LPC2104/2105/2106 Single-chip 32-bit microcontrollers Table 9. Static characteristics ...continued Tamb = 0 C to +70 C for commercial applications, unless otherwise specified. Symbol IDD(act) Parameter active mode supply current Conditions VDD(1V8) = 1.8 V; CCLK = 60 MHz; Tamb = 25 C; code Min Typ[1] 35 Max Unit mA LPC2104/2105/2106 and LPC2104/2105/2106/00 power consumption while(1){} executed from flash; all peripherals enabled via PCONP register but not configured to run IDD(pd) Power-down mode supply current VDD(1V8) = 1.8 V; Tamb = 25 C, VDD(1V8) = 1.8 V; Tamb = 85 C LPC2104/2105/2106/01 power consumption IDD(act) active mode supply current VDD(1V8) = 1.8 V; CCLK = 60 MHz; Tamb = 25 C; code 40 mA 10 50 500 A A while(1){} executed from flash; all peripherals enabled via PCONP register but not configured to run[11] IDD(idle) Idle mode supply current VDD(1V8) = 1.8 V; CCLK = 60 MHz; Tamb = 25 C; executed from flash; all peripherals enabled via PCONP register but not configured to run[11] IDD(pd) Power-down mode supply current VDD(1V8) = 1.8 V; Tamb = 25 C, VDD(1V8) = 1.8 V; Tamb = 85 C I2C-bus pins VIH VIL Vhys VOL ILI HIGH-state input voltage LOW-state input voltage hysteresis voltage LOW-state output voltage input leakage current IOLS = 3 mA VI = VDD(3V3) VI = 5 V [7] [12] - 7 - mA - 10 - 300 A A 0.7VDD(3V3) - 2 10 - V V V A A 0.3VDD(3V3) V 0.4 4 22 0.5VDD(3V3) - LPC2104_2105_2106_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 20 June 2008 28 of 41 NXP Semiconductors LPC2104/2105/2106 Single-chip 32-bit microcontrollers Table 9. Static characteristics ...continued Tamb = 0 C to +70 C for commercial applications, unless otherwise specified. Symbol Vi(XTAL1) Vo(XTAL2) Parameter input voltage on pin XTAL1 output voltage on pin XTAL2 Conditions Min 0 0 Typ[1] Max 1.8 1.8 Unit V V Oscillator pins [1] [2] [3] [4] [5] [6] [7] [8] [9] Typical ratings are not guaranteed. The values listed are at room temperature (+25 C), nominal supply voltages. Internal rail. External rail. Including voltage on outputs in 3-state mode. VDD(3V3) supply voltages must be present. 3-state outputs go into 3-state mode when VDD(3V3) is grounded. Accounts for 100 mV voltage drop in all supply lines. Allowed as long as the current limit does not exceed the maximum current allowed by the device. Minimum condition for VI = 4.5 V, maximum condition for VI = 5.5 V. [10] Applies to P0[31:22]. [11] SPI is enabled and SSP is disabled in the PCONP register (see LPC2104/2105/2106 user manual). [12] To VSS. 8.1 Power consumption measurements for LPC2104/2105/2106/01 The power consumption measurements represent typical values for the given conditions. The peripherals were enabled through the PCONP register, but for these measurements the peripherals were not configured to run. Power measurements with all peripherals enabled were performed with the SPI enabled and the SSP disabled. Peripherals were disabled through the PCONP register. Refer to the LPC2104/2105/2106 User Manual for a description of the PCONP register. 60 IDD(act) (mA) all peripherals enabled 40 all peripherals disabled 002aad709 20 0 12 28 44 frequency (MHz) 60 Test conditions: Active mode entered executing code from on-chip flash; PCLK = CCLK4; Tamb = 25 C; core voltage 1.8 V. Fig 5. LPC2104_2105_2106_7 Typical LPC2104/2105/2106/01 IDD(act) measured at different frequencies (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 20 June 2008 29 of 41 NXP Semiconductors LPC2104/2105/2106 Single-chip 32-bit microcontrollers 60 IDD(act) (mA) 40 002aad710 60 MHz 48 MHz 20 12 MHz 0 1.65 1.70 1.75 1.80 1.85 1.90 1.95 core voltage (V) Test conditions: Active mode entered executing code from on-chip flash; PCLK = CCLK4; Tamb = 25 C; all peripherals enabled. Fig 6. Typical LPC2104/2105/2106/01 IDD(act) measured at different core voltages 15.0 IDD(idle) (mA) 10.0 002aad711 all peripherals enabled all peripherals disabled 5.0 0.0 12 28 44 frequency (MHz) 60 Test conditions: Idle mode entered executing code from on-chip flash; PCLK = CCLK4; Tamb = 25 C; core voltage 1.8 V. Fig 7. Typical LPC2104/2105/2106/01 IDD(idle) measured at different frequencies LPC2104_2105_2106_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 20 June 2008 30 of 41 NXP Semiconductors LPC2104/2105/2106 Single-chip 32-bit microcontrollers 15.0 IDD(idle) (mA) 10.0 60 MHz 48 MHz 5.0 12 MHz 002aad712 0.0 1.65 1.70 1.75 1.80 1.85 1.90 1.95 core voltage (V) Test conditions: Idle mode entered executing code from on-chip flash; PCLK = CCLK4; Tamb = 25 C; all peripherals enabled. Fig 8. Typical LPC2104/2105/2106/01 IDD(idle) measured at different core voltages 45 60 MHz IDD(act) (mA) 35 48 MHz 002aad713 25 15 12 MHz 5 -40 -15 10 35 60 85 temperature (C) Test conditions: Active mode entered executing code from on-chip flash; PCLK = CCLK4; core voltage 1.8 V; all peripherals disabled. Fig 9. Typical LPC2104/2105/2106/01 IDD(act) measured at different temperatures LPC2104_2105_2106_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 20 June 2008 31 of 41 NXP Semiconductors LPC2104/2105/2106 Single-chip 32-bit microcontrollers 6.0 60 MHz IDD(Idle) (mA) 48 MHz 4.0 002aad714 2.0 12 MHz 0.0 -40 -15 10 35 60 85 temperature (C) Test conditions: Idle mode entered executing code from on-chip flash; PCLK = CCLK4; core voltage 1.8 V; all peripherals disabled. Fig 10. Typical LPC2104/2105/2106/01 IDD(idle) measured at different temperatures 300 IDD(pd) (A) 200 1.95 V 1.80 V 1.65 V 002aad715 100 0 -40 -15 10 35 60 85 temperature (C) Test conditions: Power-down mode entered executing code from on-chip flash. Fig 11. Typical LPC2104/2105/2106/01 core power-down current IDD(pd) measured at different temperatures Table 10. Typical LPC2104/2105/2106/01 peripheral power consumption in Idle mode Core voltage 1.8 V; Tamb = 25 C; all measurements in mA; PCLK = CCLK4 Peripheral Timer 0 Timer 1 UART 0 UART 1 CCLK = 60 MHz 0.258 0.254 0.494 0.561 LPC2104_2105_2106_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 20 June 2008 32 of 41 NXP Semiconductors LPC2104/2105/2106 Single-chip 32-bit microcontrollers Typical LPC2104/2105/2106/01 peripheral power consumption in Idle mode ...continued Table 10. Peripheral PWM0 I2C-bus SPI RTC SSP CCLK = 60 MHz 0.511 0.078 0.060 0.109 0.377 LPC2104_2105_2106_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 20 June 2008 33 of 41 NXP Semiconductors LPC2104/2105/2106 Single-chip 32-bit microcontrollers 9. Dynamic characteristics Table 11. Dynamic characteristics Tamb = 0 C to +70 C for commercial applications, -40 C to +85 C for industrial applications; VDD(1V8), VDD(3V3) over specified ranges.[1] Symbol External clock fosc oscillator frequency supplied by an external oscillator (signal generator) external clock frequency supplied by an external crystal oscillator external clock frequency if on-chip PLL is used external clock frequency if on-chip bootloader is used for initial code download Tcy(clk) tCHCX tCLCX tCLCH tCHCL tr tf I2C-bus tf [1] [2] Parameter Conditions Min 1 1 Typ - Max 25 25 Unit MHz MHz 10 10 - 25 25 MHz MHz clock cycle time clock HIGH time clock LOW time clock rise time clock fall time rise time fall time pins (P0.2 and P0.3) fall time VIH to VIL [2] 20 Tcy(clk) x 0.4 Tcy(clk) x 0.4 - 10 10 1000 5 5 - ns ns ns ns ns ns ns ns Port pins (except P0.2 and P0.3) 20 + 0.1 x Cb - Parameters are valid over operating temperature range unless otherwise specified. Bus capacitance Cb in pF, from 10 pF to 400 pF. LPC2104_2105_2106_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 20 June 2008 34 of 41 NXP Semiconductors LPC2104/2105/2106 Single-chip 32-bit microcontrollers 9.1 Timing tCHCL tCLCX Tcy(clk) tCHCX tCLCH 002aaa907 Fig 12. External clock timing (with an amplitude of at least Vi(RMS) = 200 mV) LPC2104_2105_2106_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 20 June 2008 35 of 41 NXP Semiconductors LPC2104/2105/2106 Single-chip 32-bit microcontrollers 10. Package outline LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm SOT313-2 c y X 36 37 25 24 ZE A e E HE A A2 A1 (A 3) Lp L detail X wM pin 1 index 48 1 12 ZD bp D HD wM B vM B vM A 13 bp e 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.6 A1 0.20 0.05 A2 1.45 1.35 A3 0.25 bp 0.27 0.17 c 0.18 0.12 D (1) 7.1 6.9 E (1) 7.1 6.9 e 0.5 HD 9.15 8.85 HE 9.15 8.85 L 1 Lp 0.75 0.45 v 0.2 w 0.12 y 0.1 Z D (1) Z E (1) 0.95 0.55 0.95 0.55 7 o 0 o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT313-2 REFERENCES IEC 136E05 JEDEC MS-026 JEITA EUROPEAN PROJECTION ISSUE DATE 00-01-19 03-02-25 Fig 13. Package outline SOT313-2 (LQFP48) LPC2104_2105_2106_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 20 June 2008 36 of 41 NXP Semiconductors LPC2104/2105/2106 Single-chip 32-bit microcontrollers HVQFN48: plastic thermal enhanced very thin quad flat package; no leads; 48 terminals; body 7 x 7 x 0.85 mm SOT619-1 D B A terminal 1 index area A E A1 c detail X e1 e 13 L 12 25 e 1/2 e C b 24 vMCAB wMC y1 C y Eh 1/2 e e2 1 terminal 1 index area 48 Dh 0 DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max. 1 A1 0.05 0.00 b 0.30 0.18 c 0.2 D (1) 7.1 6.9 Dh 5.25 4.95 E (1) 7.1 6.9 Eh 5.25 4.95 e 0.5 37 36 X 2.5 scale e1 5.5 e2 5.5 L 0.5 0.3 v 0.1 w 0.05 y 0.05 y1 0.1 5 mm Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. OUTLINE VERSION SOT619-1 REFERENCES IEC --JEDEC MO-220 JEITA --EUROPEAN PROJECTION ISSUE DATE 01-08-08 02-10-18 Fig 14. Package outline SOT619-1 (HVQFN48) LPC2104_2105_2106_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 20 June 2008 37 of 41 NXP Semiconductors LPC2104/2105/2106 Single-chip 32-bit microcontrollers 11. Abbreviations Table 12. Acronym AMBA APB CPU DCC FIFO GPIO PLL PWM RAM SPI SSI SSP SRAM TTL UART Abbreviations Description Advanced Microcontroller Bus Architecture ARM Peripheral Bus Central Processing Unit Debug Communications Channel First In, First Out General Purpose Input/Output Phase-Locked Loop Pulse Width Modulator Random Access Memory Serial Peripheral Interface Synchronous Serial Interface Synchronous Serial Port Static Random Access Memory Transistor-Transistor Logic Universal Asynchronous Receiver/Transmitter LPC2104_2105_2106_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 20 June 2008 38 of 41 NXP Semiconductors LPC2104/2105/2106 Single-chip 32-bit microcontrollers 12. Revision history Table 13. Revision history Release date 20080620 Data sheet status Product data sheet Change notice Supersedes LPC2104_2105_2106_6 Document ID LPC2104_2105_2106_7 Modifications: * * * * * * * * * The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. Section 3 "Ordering information"; corrected temperature range for LPC2104FBD48/00, LPC2105FBD48/00. Parts LPC2104FBD48/01, LPC2105FBD48/01, LPC2106BBD48, LPC2106FBD48/01, and LPC2106FHN48/01 added. Description of /01 features added. LPC2104/2105/2106/01 power consumption measurements added. Maximum frequency fosc for external oscillator and external crystal updated. Figure 12 "External clock timing (with an amplitude of at least Vi(RMS) = 200 mV)" updated. Condition for IOHS and IOLS updated in Table 9 "Static characteristics". Product data sheet Product data Product data Product data Product data Product data LPC2104_2105_2106-05 LPC2104_2105_2106-04 LPC2104_2105_2106-03 LPC2104_2105_2106-02 LPC2104_2105_2106-01 - LPC2104_2105_2106_6 LPC2104_2105_2106-05 LPC2104_2105_2106-04 LPC2104_2105_2106-03 LPC2104_2105_2106-02 LPC2104_2105_2106-01 20060725 20041222 20040205 20031007 20030611 20030425 LPC2104_2105_2106_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 20 June 2008 39 of 41 NXP Semiconductors LPC2104/2105/2106 Single-chip 32-bit microcontrollers 13. Legal information 13.1 Data sheet status Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 13.2 Definitions Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 13.3 Disclaimers General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected 13.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus -- logo is a trademark of NXP B.V. 14. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com LPC2104_2105_2106_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 20 June 2008 40 of 41 NXP Semiconductors LPC2104/2105/2106 Single-chip 32-bit microcontrollers 15. Contents 1 2 2.1 2.2 3 3.1 4 5 5.1 5.2 6 6.1 6.2 6.3 6.4 6.5 6.5.1 6.6 6.7 6.8 6.9 6.9.1 6.9.2 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 New features implemented in LPC2104/2105/2106/01 devices. . . . . . . . . . . . 1 Key common features . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 3 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 7 Functional description . . . . . . . . . . . . . . . . . . 10 Architectural overview. . . . . . . . . . . . . . . . . . . 10 On-chip flash program memory . . . . . . . . . . . 10 On-chip static RAM. . . . . . . . . . . . . . . . . . . . . 10 Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . 11 Interrupt controller . . . . . . . . . . . . . . . . . . . . . 12 Interrupt sources. . . . . . . . . . . . . . . . . . . . . . . 12 Pin connect block . . . . . . . . . . . . . . . . . . . . . . 13 Pin function select register 0 (PINSEL0 0xE002 C000). . . . . . . . . . . . . . . . . . . . . . . . . 13 Pin function select register 1 (PINSEL1 0xE002 C004). . . . . . . . . . . . . . . . . . . . . . . . . 15 General purpose parallel I/O. . . . . . . . . . . . . . 16 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Features added with the Fast GPIO set of registers available on LPC2104/2105/2106/01 only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 UARTs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 UART features available in LPC2104/2105/2106/01 only . . . . . . . . . . . . . 17 I2C-bus serial I/O controller . . . . . . . . . . . . . . 17 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 SPI serial I/O controller. . . . . . . . . . . . . . . . . . 18 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Features available in LPC2104/2105/2106/01 only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 SSP controller (LPC2104/2015/2106/01 only) 18 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 General purpose timers . . . . . . . . . . . . . . . . . 18 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Features available in LPC2104/2105/2106/01 only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Watchdog timer. . . . . . . . . . . . . . . . . . . . . . . . 19 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Real time clock . . . . . . . . . . . . . . . . . . . . . . . . 20 6.16.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.17 Pulse width modulator . . . . . . . . . . . . . . . . . . 6.17.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.18 System control . . . . . . . . . . . . . . . . . . . . . . . . 6.18.1 Crystal oscillator. . . . . . . . . . . . . . . . . . . . . . . 6.18.2 PLL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.18.3 Reset and wake-up timer . . . . . . . . . . . . . . . . 6.18.4 Code security (Code Read Protection - CRP) 6.18.5 External interrupt inputs . . . . . . . . . . . . . . . . . 6.18.6 Memory mapping control . . . . . . . . . . . . . . . . 6.18.7 Power control . . . . . . . . . . . . . . . . . . . . . . . . . 6.18.8 APB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.19 Emulation and debugging. . . . . . . . . . . . . . . . 6.19.1 EmbeddedICE . . . . . . . . . . . . . . . . . . . . . . . . 6.19.2 Embedded trace. . . . . . . . . . . . . . . . . . . . . . . 6.19.3 RealMonitor . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 8 Static characteristics . . . . . . . . . . . . . . . . . . . 8.1 Power consumption measurements for LPC2104/2105/2106/01 . . . . . . . . . . . . . . . . . 9 Dynamic characteristics . . . . . . . . . . . . . . . . . 9.1 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 11 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 12 Revision history . . . . . . . . . . . . . . . . . . . . . . . 13 Legal information . . . . . . . . . . . . . . . . . . . . . . 13.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 13.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 13.4 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Contact information . . . . . . . . . . . . . . . . . . . . 15 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 20 21 21 21 21 22 22 23 23 23 23 24 24 24 25 26 27 29 34 35 36 38 39 40 40 40 40 40 40 41 6.10 6.10.1 6.10.2 6.11 6.11.1 6.12 6.12.1 6.12.2 6.13 6.13.1 6.14 6.14.1 6.14.2 6.15 6.15.1 6.16 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'. (c) NXP B.V. 2008. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 20 June 2008 Document identifier: LPC2104_2105_2106_7 |
Price & Availability of LPC2104BBD48
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